1. Field of the Invention
The present invention relates to an electronic circuit for sensing the logic state of a memory cell, and in particular to a sense amplifier and associated circuitry for reading data from a flash memory circuit that operates in a current mode.
2. Description of the Related Art
Common types of non-volatile memory, such as EPROM (Electrically Programmable Read Only Memory), EEPROM (Electrically Erasable Programmable Read Only Memory) and Flash memory use a charge on a memory cell's floating gate to control the threshold voltage (Vt) of the memory cell and thereby indicate the binary state of the cell. Typically, such memory cells have two possible binary states, one (e.g. "0") indicated by a high threshold voltage and one (e.g. "1") indicated by a low threshold voltage. Gathering electrons on a memory cell's floating gate increases the cell's threshold voltage and is referred to as writing or programming the memory cell. Erasing a memory cell removes the electrons from the floating gate and reduces the threshold voltage.
A Flash memory is an integrated circuit that includes an array of electrically programmable and electrically erasable memory cells. A basic flash memory cell 100 is shown in FIG. 1A. Flash memory cell 100 includes an access transistor 110 and a double-polysilicon storage transistor 120. Storage transistor 120 has a floating polysilicon gate 122 that is isolated in silicon dioxide and capacitively coupled to a polysilicon control gate 124. Storage transistor 120 also has a region of silicon dioxide between the floating gate 122 and a drain 126 that is thin enough to permit electrons to tunnel to and from floating gate 122 when the proper bias voltages are applied to the terminals of storage transistor 120.
As shown in FIG. 1A, storage transistor 120 is programmed by grounding its source 128, applying approximately 5 to 6 volts to its drain 126, and connecting its control gate 124 to a programming voltage Vpp that is high relative to the operating voltage Vcc. A typical value for Vpp is 12 volts, while a typical value for Vcc is 5 volts. With storage transistor 120 biased by the application of Vpp, electrons travel through the tunnel oxide to the floating gate 122, leaving the floating gate 122 with a net negative charge. This net negative charge shifts the threshold voltage Vt of storage transistor 120 in the positive direction to a voltage that is greater than Vcc.
As shown in FIG. 1B, storage transistor 120 is erased by grounding control gate 124 and applying a relatively high voltage (e.g., 12 volts) to the source 128. This bias allows electrons to tunnel away from the floating gate 122 through the tunnel oxide to be carried away by the large positive voltage on source 128. The loss of electrons on the floating gate 122 shifts the threshold voltage Vt of storage transistor 120 in the negative direction to a voltage that is less than Vcc.
When erasing storage transistor 120, it is possible to remove too many electrons from floating gate 122, resulting in excess positive charge on floating gate 122. This condition is commonly known as "over-erase." Access transistor 110 is provided to prevent storage transistor 120, in the event that storage transistor 120 is over-erased, from conducting as a result of excess positive charge on floating gate 122.
After flash memory cell 100 is programmed or erased, the state of the storage transistor may then be "read" by determining whether the storage transistor conducts when access transistor 110 is turned on by application of a voltage to the gate of access transistor 110. If the storage transistor 120 is programmed, i.e., there is a net negative charge on floating gate 122, storage transistor 120 will not conduct when access transistor 110 is turned on since the threshold voltage Vt is a voltage greater than Vcc. If, on the other hand, the storage transistor is erased, i.e., there is no charge on floating gate 122, storage transistor 120 will conduct when access transistor 110 is turned on since the threshold voltage Vt is less than Vcc.
As shown in FIG. 1C, sense amplifier 150, coupled across the series connected access transistor 110 and storage transistor 120 of cell 100, determines whether storage transistor 120 conducts based upon the current that flows through the sense amplifier 150. A signal corresponding to the state of cell 100, i.e., either a logic high or a logic low, as read by the sense amplifier 150 is output on line 152.
However, there are problems with the conventional current mode sense amplifiers used to sense whether the storage transistor 120 conducts or not, i.e., whether there is any current flow. Since the amount of current that will flow if the cell 100 has been erased is relatively small, the sense amplifier must be sensitive enough to determine whether the threshold current indicating the cell 100 is erased has been exceeded. This increased sensitivity makes the sense amplifier subject to possible erroneous readings caused by noise signals. A spurious noise signal may cause minute currents to flow into sense amplifier 150 during a read operation, causing the sense amplifier 150 to erroneously determine that cell 100 has been erased. Thus there exists the need for a current mode sense amplifier that provides increased immunity to noise signals to prevent erroneous readings.